A conventional differential amplifying apparatus is configured as shown in FIG. 9 or 11.
In the following description, a "P channel MOS transistor" is represented as a "P-ch transistor". An "N channel MOS transistor" is represented as an "N-ch transistor".
First, the differential amplifying apparatus shown in FIG. 9 is explained.
This differential amplifying apparatus is composed of a differential circuit 1; an output circuit 2; a bias voltage generating circuit composed of a P-ch transistor and a resistor R; and a controlling P-ch transistor that connects a bias voltage VBIAS to a power supply voltage to turn off the current through the differential circuit 1 and output circuit 2.
The differential circuit 1 is composed of P-ch transistors 601, 602, and 603 and N-ch transistors 604 and 605.
The P-ch transistor 601 has its source connected to a power supply voltage VDD to provide the constant bias VBIAS to its gate in order to function as a constant current source.
The sources of the two P-ch transistors 602 and 603 are both connected to the drain of the P-ch transistor 601. The drain of the N-ch transistor 604 is connected to the drain of the P-ch transistor 602, and the drain of the N-ch transistor 605 is connected to the drain of the P-ch transistor 603.
The sources of the N-ch transistors 604 and 605 are connected together for grounding, and the gates of these transistors are connected together and to the drain of the P-ch transistor 603, that is, the drain of the N-ch transistor 605.
In the output circuit 2, the source of the constant-current source transistor 606 consisting of a P-ch transistor is connected to the power supply voltage VDD, and the constant bias VBIAS is applied to the gate of the constant-current source transistor 606. The drain of the controlling transistor 607 consisting of an N-ch transistor is connected to the drain of the constant-current source transistor 606, the source of the controlling transistor 607 is grounded, and the gate of the controlling transistor 607 is connected to the drain of the P-ch transistor 602 that is an output terminal of the differential circuit 1.
The P-ch transistor 608 constituting a bias voltage generating circuit has its source connected to the power supply voltage VDD and its gate connected to its drain. The drain terminal is grounded via a resistor 610.
In the connection between the P-ch transistor 608 and resistor 610, a constant voltage is determined by design parameters such as the width and length of the gate of the P-ch transistor 608 and the resistance value of the resistor 610. This voltage VBIAS is supplied as a gate voltage for the transistor for biasing the differential circuit 1 and output circuit 2.
If the differential amplifying apparatus in FIG. 9 is applied to a TFT liquid crystal driving apparatus, as many circuits as the pixels are required. Thus, several-hundred differential circuits must be arranged in the same semiconductor apparatus.
To reduce increasing current consumption, the P-ch transistor 608 and resistor 610 must be designed to provide a minimum amount of current required. Thus, in the differential circuit used for the liquid crystal driving apparatus, the bias voltage VBIAS is relatively close to the power supply voltage (.apprxeq.VDD-1 volt) and several-ten K.OMEGA. is selected as the resistance value R to provide a low current.
The P-ch transistor 609 has its source connected to the power supply voltage VDD, its gate connected to a standby control signal STBY, and its drain connected to the bias voltage VnIAS. Reference numeral 611 designates a parasitic capacitance generated in the wiring for the bias voltage signal VBIAS and represented by a capacitance value C1.
Next, the operation of the differential amplifying apparatus shown in FIG. 9 is described with reference to FIG. 10.
In a normal state, the standby control signal STBY is at an "H" level and the P-ch transistor 609 is turned off. Thus, the bias voltage VBIAS is generated and determined by the P-ch transistor 608 and resistor 610.
The differential circuit 1 has an inverting input terminal V- and a non-inverting input terminal V+. The inverting input terminal is connected to an output terminal Vo, and the differential circuit 1 and output circuit 2 constitute a null amplifier. Thus, if a Vin signal is input to the non-inverting input terminal V+, a voltage almost the same as Vin is generated at the output terminal Vo.
Next, the STBY signal is changed to an "L" level. Then, the P-ch transistor 609 is turned on to increase the bias voltage VBIAS up to the power supply voltage VDD.
The voltage VrIAS is set at about (VDD-1 voltage) due to a low-current-consumption design. Thus, the voltage can be increased up to the power supply voltage at a high speed depending on the designed size of the P-ch transistor 609.
At this point, the gate voltages of the P-ch transistor 601 in the differential circuit 1 and the P-ch transistor 606 in the output circuit 2 increase up to the power supply voltage VDD to prevent a current from flowing through the transistors 601 and 606. Thus, the differential circuit 1 and output circuit 2 consume no current and are in a standby state. The voltage at the output terminal Vo becomes indeterminate.
Next, the STBY signal is changed to an "H" level to switch the standby state to a normal operation state. This causes the P-ch transistor 609 to be turned off. VBIAS, which has increased up to the power supply voltage, has the parasitic capacitance 611 of the capacitance value C1 in which charges constituting the power supply potential are accumulated. The resistance value R of the resistor 610 serves to discharge the charges accumulated in the parasitic capacitance and to reduce VBIAS down to the normal operation potential (.apprxeq.VDD-1 voltage).
FIG. 11 shows another conventional differential amplifying apparatus.
In the differential amplifying apparatus in FIG. 11, the P-ch transistors of the differential and output circuits 1 and 2 shown in FIG. 9 are replaced by N-ch transistors.
The differential circuit 3 is composed of N-ch transistors 701, 702, and 703 and P-ch transistors 704 and 705.
The N-ch transistor 701 has its source connected to VSS to provide a constant bias VBIAN to its gate in order to function as a constant current source.
The sources of the two N-ch transistors 702 and 703 are both connected to the drain of the N-ch transistor 701. The drain of the P-ch transistor 704 is connected to the drain of the N-ch transistor 702, and the drain of the P-ch transistor 705 is connected to the drain of the N-ch transistor 703.
The sources of the P-ch transistors 704 and 705 are connected together and to the power supply voltage VDD, and the gates of these transistors are connected together and to the drain of the N-ch transistor 703, that is, the drain of the P-ch transistor 705.
The output circuit 4 is composed of the N-ch transistor 706 and the P-ch transistor 707. The N-ch transistor 706 has its source grounded to provide the constant bias VBIASN to its gate in order to function as a constant current source.
The drain of the P-ch transistor 707 is connected to the drain of the N-ch transistor 706, and the P-ch transistor 707 has its source connected to the power supply voltage VDD and its gate connected to the drain of the N-ch transistor 702 that is an output terminal of the differential circuit 3.
The P-ch transistor 608 constituting a bias voltage generating circuit has its source connected to the power supply voltage VDD and its gate connected to its drain. The drain terminal is grounded via the resistor 610. In the connection between the P-ch transistor 608 and resistor 610, a constant voltage is determined by design parameters such as the width and length of the gate of the P-ch transistor 608 and the resistance value R of the resistor 610.
This voltage VBIAS is supplied as a gate voltage for the transistor for biasing the differential circuit 3 and output circuit 4. The bias voltage VBIAS is connected to the gate of the P-ch transistor 708, and the P-ch transistor 708 has its source connected to the power supply voltage VDD and its drain connected to the drain of the N-ch transistor 709. The N-ch transistor 709 has its gate connected to its drain and its source grounded.
The drain of the N-ch transistor 709 is supplied as the bias voltage VBIASN to the gates of the N-ch transistor 701 in the differential circuit 3 and the N-ch transistor 706 in the output circuit 4.
As in FIG. 9, the bias circuit is designed for VBIASN that can prevent a large amount of currents from being consumed.
The P-ch transistor 609 has its source connected to the power supply voltage VDD, its gate connected to the standby control signal STBY, and its drain connected to the bias voltage VBIAS. Reference numeral 710 designates a parasitic capacitance generated in the wiring for the bias voltage signal VBIASN and represented as a capacitance value C3.
FIG. 12 is a timing chart of FIG. 11.
In a normal state, the standby control signal STBY is at an "H" level and the P-ch transistor 609 is turned off. Thus, the bias voltage VBIAS is generated and determined by the P-ch transistor 608 and resistor 610. In addition, the P-ch and N-ch transistors 708 and 709 generate the bias voltage VBIASN. The differential circuit 3 and output circuit 4 constitute a null amplifier, as in FIG. 9. Thus, if the Vin signal is input to the non-inverting input terminal V+, a voltage almost the same as Vin is generated at the output terminal Vo.
Next, the STBY signal is changed to an "L" level. Then, the P-ch transistor 609 is turned on to increase the bias voltage VBIAS up to the power supply voltage VDD. In addition, the gate voltage of the P-ch transistor 708 increases up to the power supply voltage VDD to prevent a current from flowing, thereby reducing the operating drain voltage of the N-ch transistor 709 down to VSS and thus reducing VBIASN down to VSS.
The voltage VBIASN is set at about (VSS+1 voltage) due to the low-current-consumption design. Thus, the voltage can be reduced down to VSS at a high speed depending on the designed size of the N-ch transistor 709.
At this point, the gate voltages of the N-ch transistor 701 in the differential circuit 3 and the N-ch transistor 706 in the output circuit 4 decrease down to VSS to prevent a current from flowing through the N-ch transistors 701 and 706. Thus, the differential circuit 3 and output circuit 4 consume no current and are in a standby state. The voltage at the output terminal Vo becomes indeterminate.
Next, the STBY signal is changed to an "H" level to switch the standby state to the normal operation state. This causes the P-ch transistor 609 to be turned off. VBIASN, which has decreased down to VSS, has a parasitic capacitance 710 in which charges constituting the VSS potential are accumulated. Since the resistance of the P-ch transistor 708 is set at a large value due to the low-current-consumption design, a desired amount of charges are filled in the parasitic capacitance to increase VBIASN up to the normal operating potential (.apprxeq.VSS+1 voltage).